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IGNOU MCS-12 - Computer Organization and ALP , Latest Solved Assignment (July 2023 - January 2024)

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IGNOU MCS-12 July 2023 - January 2024 - Solved Assignment

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IGNOU MCS-12 (July 2023 - January 2024) Assignment Questions

Q1: (a) Please refer to Figure 4 of Unit 1 of Block 1 on page 11 of Instruction execution example. Assuming a similar machine is to be used for execution of the following three consecutive instructions: LOAD A ; Load the content of Memory location A into the Accumulator Register. ADD B ; Add the content of memory location B from Accumulator Register. STOR C ; Stores the content of the Accumulator register to memory location C However, this machine is different from the example of Figure 4 in the following ways: • Each memory word of this new machine is of 16 bits in length. • Each instruction is of length 32 bits with 16 bits for operation code (opcode) and 16 bits for specifying one direct operand. • The Main Memory of the machine would be of size 2 16 words. • The three consecutive instructions are placed starting from memory location (11FE)h ; operand A is at location (1FFF)h and contains a value (4321)h, Operand B is at location (2000)h and contains a value (1FFE)h and operand C is at location (2001)h and contains a value (0000)h. • The AC, PC, MAR and MBR registers are of size 16 bits, whereas IR register is of size 32 bits. The initial content of PC register is (11FE)h Draw the diagrams showing the following information: (i) Initial State of the machine with the addresses and content of memory locations in hexadecimal. Show only those address locations of the memory that store the instruction and data. Also, show the content of all the stated registers. (ii) Draw three more diagrams, each showing the state of the machine after execution of every instruction viz. LOAD, ADD and STOR. Show the changes in the values of Registers and memory locations, if any, due to the execution of the instruction. Show all the addresses and values in hexadecimal notations

(b) Perform the following conversion of numbers:

i) Decimal (345654398)10 to binary and hexadecimal ii) Hexadecimal (FFEEDDCBA)h into Octal. iii) String “Computer Organisation” into UTF 8 iv) Octal (6754632)O into Decimal

(c) Simplify the following function using K-map: F(A, B, C, D) = Σ (1, 3, 4, 7, 11, 13) Draw the circuit for the function using NAND gates

(d) Consider the Adder-Sub tractor circuit as shown in Figure 3.15 page 76 of Block 1. Explain how this circuit will perform subtraction (A-B), if the value of A is 1011 and B is 0011. You must list all the bit values including Cin and Cout and overflow, if any

(e) Explain the functioning of a 3 × 8 decoder with the help of a logic diagram and example input.

(f) Assume that a source data value 1011 was received at a destination as 1010. Show how Hamming's Error-Correcting code bits will be appended to source data to identify and correct the error of one bit at the destination. You may assume that transmission error occurs only in the source data and not the source parity bits

(g) Explain the functioning of the D flip-flop and the T flip-flop with the help of a logic diagram and characteristic table. Also, explain the excitation table of this flip-flop.

(h) Explain the functioning of the edge-triggered flip-flop with the help of a diagram

(i) Represent (-121. 25)10 and (0. 0625)10 in IEEE 754 single-precision and double-precision formats.

Q2: (a) Refer to the Figure 2(b) on page 8 in Unit 1 of Block 2. Draw the Internal organisation of an 8×8 RAM. Explain all the Input and Output of this organisation. Also, answer the following: (i) How many data input and data output lines does this RAM need? Explain your answer. (ii)How many address lines are needed for this RAM? Give reasons in support of your answer

(b) A computer has 64 K Word RAM with each memory word of 16 bits. It has cache memory having 32 blocks having a size of 32 bits (2 memory words). Show how the main memory address (1AFC)h will be mapped to the cache address, if (i) Direct cache mapping is used (ii) Associative cache mapping is used (iii)Two-way set associative cache mapping is used. You should show the size of the tag, index, main memory block address and offset in your answer.

(c) What is an Interrupt? Why are interrupts used in a computer? Explain different kinds of interrupts. Also, explain the process of interrupt processing.

(d) What is an I/O processor? Explain the selector channel structure in the context of the I/O processor. How is an I/O processor different from DMA?

(e) Assume that a disk has 32 tracks, with each track having 16 sectors and each sector is of size 512 Kilobytes. The cluster size in this system can be assumed to be 2 sectors. A file having the name mcs012.txt is of size 16 MB. Assume that it is a new disk, and the first 8 clusters are occupied by the Operating System. Rest all the clusters are free. How can this file be allotted space on this disk? Also, show the content of FAT after the space allocation to this file. You may make suitable assumptions

(f) Explain the following, giving their uses and advantages/disadvantages, if needed. (Word limit for the answer of each part is 50 words ONLY) (i) Rotational Latency in disks (ii) Programmed I/O (iii) Resolution of Display and Printer (iv) Zip Drive (v) Power Supply (vi) Keyboard and Mouse

Q3: (a) A single-core uniprocessor system has 8 General purpose registers. The machine has RAM of size 64K memory words. The size of every general-purpose register and memory word is 16 bits. The computer uses fixed-length instructions of size 32 bits each. An instruction of the machine can have two operands. One of these operands is a direct memory operand and the other is a register operand. An instruction of a machine consists of bits for operation code, bits for memory operand and bits of register operand. The machine has about 128 different operation codes. The special purpose registers, which are other than general purpose registers, are - Program Counter (PC), Memory Address Register (MAR), Data Register (DR) and Flag registers (FR). The first register among the generalpurpose registers can be used as Accumulator Register. The size of Integer operands on the machine may be assumed to be equal to the size of the accumulator register. To execute instructions, the machine has another special register called Instruction Register (IR) of size 32 bits, as each instruction is of this size. Perform the following tasks for the machine. (Make and state suitable assumptions, if any.) (i) Design suitable instruction formats for the machine. Specify the size of different fields that are needed in the instruction format. Also, indicate how many bits of the instructions are unused for this machine. Explain your design of the instruction format. Also, indicate the size of each register. (ii) Demonstrate two valid instructions of the machine; put some valid data values in registers and memory locations and show these two instructions. (iii)Assuming that the instructions are first fetched to the Instruction Register (IR), the memory operand is brought to the DR register and the result of an operation is stored in the Accumulator register; write and explain the sequence of micro-operations that are required to fetch and execute an addition instruction that adds the contents of the memory and register operands of the instruction. The result is stored in the accumulator register. Make and state suitable assumptions, if any

(b) Assume that you have a machine, as shown in section 3.2.2 of Block 3 having the micro-operations given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are 8-bit registers and contain 11100111 and 00111100 respectively. What will be the values of select inputs, carry-in input, and the result of the operation (including carry-out bit) if the following micro-operations are performed? (For each micro-operation you may assume the initial value of R1 and R2 as given above) (i) Decrement R1 (ii) Add R1 and R2 with Carry (iii)Exclusive OR of the registers R1 and R2 (iv) Shift right R1

(c) Consider that an instruction pipeline has three stages namely instruction fetch and decode (FD), Operand Fetch (OF) and Instruction Execute and store results (ES). Draw an instruction pipeline diagram showing the execution of five sequential instructions using this pipeline. What are the problems with this instruction pipelining?

(d) Explain the functioning of the Wilkes Control Unit. Also, explain the format of the control memory with the help of a diagram.

(e) Explain the characteristics of RISC? Also, explain the RISC pipelining.

Q4: (a) Write a program using 8086 assembly Language (with proper comments) that accepts three different digits as input from the keyboard. Each digit is first converted to a binary equivalent. The binary values of these three digits are compared and the middle value is put in the AL register. This AL register is multiplied with each value of a byte array of size 6, which is stored in the memory. The result of the multiplication is stored in the same memory location. You may assume the byte array has the values 02h, 06h, 08h, 03h, 01h, 05h. Make suitable assumptions, if any.

(b) Write a NEAR subroutine using 8086 assembly Language (with proper comments) that returns the average value of the values stored in a byte array of length 3. All three values of the byte array are passed to the subroutine in the stack. You should write both the calling program and subroutine.

(c) Explain the following in the context of 8086 Microprocessor with the help of an example or a diagram: (i) Use of code segment and stack segment registers for computing the respective 20-bit addresses. (ii) Any 4 flags of the flag register of 8086 micro-processor (iii)Any four shift instructions of 8086 micro-processor

IGNOU MCS-12 (July 2022 - January 2023) Assignment Questions

Q1. (a) Please refer to Figure 4 of Unit 1 of Block 1 on page 11 of Instruction execution example. Assuming a similar machine is to be used for execution of the following three consecutive instructions: LODA A ; Load the content of Memory location A into the Accumulator Register. ADD B ; Add the content of memory location B from Accumulator Register. STOR C ; Stores the content of Accumulator register to memory location C. However, this machine is different from the example of Figure 4 in the following ways: • Each memory word of this new machine is of 64 bits in length. • Each instruction is of length 64 bits with 24 bits for operation code (opcode) and 40 bits for specifying one direct operand. • The Main Memory of the machine would be of size 240 words. • The three consecutive instructions are placed starting from memory location (000000FFFE)h ; operand A is at location (00000FFFF1)h and contains a value (0000051121)h, Operand B is at location (00000FFFF2)h and contains a value (00050048FE)h and operand C is at location (00000FFFF3)h and contains a value (0000000000)h. • The AC, IR and MBR registers are of size 64 bits, whereas PC and MAR registers are of size 40 bits. The initial content of PC register is (000000FFFE)h, Draw the diagrams showing the following information: (i) Initial State of the machine with the addresses and content of memory locations in hexadecimal. Show only those address locations of the memory that store the instruction and data. Also show content of all the stated registers. (ii) Draw three more diagrams, each showing the state of machine after execution of every instruction viz. LOAD, ADD and STOR. Show the changes in the values of Registers and memory locations, if any, due to execution of instruction. Show all the addresses and values in hexadecimal notations. (b) Perform the following conversion of numbers: i) Decimal (6545679870)10 to binary and hexadecimal ii) Hexadecimal (ABCDEFF90)h into Octal. iii) String “Assembly Language Programming” into UTF 8 iv) Octal (2345671)O into Decimal (c) Simplify the following function using K-map: F(A, B, C, D) = Σ (0, 1, 4, 5, 9, 10, 15) Draw the circuit for the resultant function using NAND gates. (d) Consider the Adder-Subtractor circuit as shown in Figure 3.15 page 76 of Block 1. Explain how this circuit will perform subtraction (A-B), if the value of A is 1001 and B is 0111. You must list all the bit values including Cin and Cout and overflow, if any. (e) Explain the functioning of a 4 × 1 multiplexer with the help of logic diagram and example input. (f) Assume that a source data value 1101 was received at a destination as 1111. Show how Hamming's Error-Correcting code bits will be appended to source data, so this error of one bit is identified and corrected at the destination. You may assume that transmission error occurs only in the source data and not the source parity bits. (g) Explain functioning of J-K flip flop with the help of a logic diagram and characteristic table. Also explain the excitation table of this flip-flop. (h) Explain the functioning of a master-slave flip-flop with the help of a diagram. (i) Represent (-49.125)10 and (0.00000025)10 in IEEE 754 single precision and double precision formats.

Q2. (a) Refer to the Figure 2(b) on page 8 in Unit 1 of Block 2. Draw the Internal organization of a 16×4 RAM. Explain all the Input and Output of this organisation. Also answer the following: (i) How many data input and data output lines does this RAM needs? Explain your answer. (ii) How many address lines are needed for this RAM? Give reason in support of your answer. (b) A computer has 1 MB RAM with each memory word of 8 bits. It has cache memory having 256 blocks having a size of 64 bits (8 memory words). Show how the main memory address (03FAC)h will be mapped to cache address, if (i) Direct cache mapping is used (ii) Associative cache mapping is used (iii)Two way set associative cache mapping is used. You should show the size of tag, index, main memory block address and offset in your answer. (c) Explain the process of interrupt handling with the help of a diagram. (d) What is DMA? Explain with the help of a flowchart. Differentiate between the working of DMA and I/O processor. (e) Assume that a disk has 256 tracks, with each track having 64 sectors and each sector is of size 1 M bits. The cluster size in this system can be assumed to be as 4 sectors. A file having the name bcaassignment.txt is of size 32 MB. Assume that disk has 64 free - continuous clusters. How can this file be allotted space on the disk? Also show the content of FAT after the space allocation to this file. You may make suitable assumptions (f) Explain the following, giving their uses and advantages/disadvantages, if needed. (6) (Word limit for answer of each part is 100 words ONLY) (i) Programmed Input/Output (ii) Access time computation on Hard disk (iii) CD-ROM (iv) Resolution of a scanner (v) Printer Technology (vi) Capacitor-based Keyboards

Q3. (a) A single core uniprocessor system has 16 general purpose registers. The machine has 1MB RAM. The size of every general purpose register and memory word is 32 bits. The computer uses fixed length instructions of size 32 bits each. An instruction of the machine can have two operands. One of these operands is a direct memory operand and other is a register operand. Both these operands use direct addressing. An instruction of a machine consists of bits for operation code, bits for memory operand and bits of register operand. The machine has about 64 different operation codes. The special purpose registers, which are other than general purpose registers, are - Program Counter (PC), Memory Address Register (MAR), Data Register (DR) and Flag registers (FR). The first register of the general-purpose registers can be used as Accumulator Register. The size of Integer operands on the machine may be assumed to be equal to the size of accumulator register. In order to execute instructions, the machine has another special register called Instruction Register (IR) of size 32 bits, as each instruction is of this size. Perform the following tasks for the machine. (Make and state suitable assumptions, if any.) (i) Design suitable instruction formats for the machine. Specify the size of different fields that are needed in the instruction format. Also indicate how many bits of the instructions are unused for this machine. Explain your design of instruction format. Also indicate the size of each register. (ii) Demonstrate two valid instructions of the machine; put some valid data values in registers and memory locations and show the execution of these two instructions. (iii) Assuming that the instructions are first fetched to Instruction Register (IR), memory operand is brought to DR register and result of an operation is stored in the Accumulator register; write and explain the sequence of micro-operations that are required to fetch and execute an instruction, which performs addition of a memory operand and a register operand. The result is stored in the accumulator register. Make and state suitable assumptions, if any. (b) Assume that you have a machine, as shown in section 3.2.2 of Block 3 having the micro-operations given in Figure 10 on page 62 of Block 3. Consider that R1 and R2 both are 8 bit registers and contains 10100101 and 11000110 respectively. What will be the values of select inputs, carry-in input and result of operation (including carry out bit) if the following micro-operations are performed? (For each micro-operation you may assume the initial value of R1 and R2 as given above) (i) Increment R1 (ii) Subtract R2 from R1 (iii) Exclusive OR of R1 and R2 (iv) Shift left R1 (c) Consider that an instruction pipeline has five stages namely instruction fetch (F), Instruction Decode (D), Operand Fetch (O), Instruction Execute (E) and store results (S). Draw an instruction pipeline diagram showing execution of five sequential instructions using this pipeline. What are the problems of this instruction pipelining? (d) Explain the functioning of micro-programmed control unit with the help of a diagram. Is Wilkes control Unit uses microprogramming? Explain. (e) Explain the use of large register file in RISC? Also, explain the optimisation of RISC pipelining.

Q4. (a) Write a program using 8086 assembly Language (with proper comments) that accepts four different digits input from the keyboard. Each digit is first converted to binary equivalent and then smallest of these digits is put in AL register. This AL register is to be added in each value of a byte array of size 9, which is stored in the memory. You may assume the byte array has the value 01h, 03h 02h, 03h, 00h, 01h, 02h, 01h, 04h. Make suitable assumptions, if any (b) Write a NEAR subroutine using 8086 assembly Language (with proper comments) that returns the largest value in a byte array of length 4-bytes. All the four values of the byte array are passed to the subroutine in a stack. You should write both the calling program and subroutine. (c) Explain the following in the context of 8086 Microprocessor: (i) Use of segment registers with the help of example (ii) Interrupt handling in 8086 micro-processor (iii) Any four bit manipulation instructions in 8086 micro-processor

MCS-12 Assignment Details

• University IGNOU (Indira Gandhi National Open University)
• Title Computer Organization and ALP
• Language(s) English
• Session July 2023 - January 2024
• Code MCS-12
• Subject Computer Application
• Degree(s) MCA , BCA
• Course Core Courses (CC)
• Author Gullybaba.com Panel
• Publisher Gullybaba Publishing House Pvt. Ltd.

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• 30th April  (if Enrolled in the June Exams)
• 31st October (if Enrolled in the December Exams).

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• July 2023 - January 2024 62 Pages (0.00 ), PDF Format SKU: IGNGB-AS-BCA-MCS12-EN-396
• July 2022 - January 2023 29 Pages (0.00 ), PDF Format SKU: IGNGB-AS-BCA-MCS12-EN-231

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Candidate Candids – Bryce Blankenship

A conversation with Moscow City Council Candidate, Bryce Blankenship.

Interviewer: Aiden Anderson

Election: Moscow City Council Seat, 2023

Note: This video and its contents is to be used in its entirety and for informational purposes only.

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